Domino logic keeper circuit design techniques: a review
By: Angeline, A. Anita
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Contributor(s): Bhaaskaran, V. S. Kanchana.
Publisher: New York Springer 2022Edition: Vol.103(2), Apr.Description: 669-679p.Subject(s): Humanities and Applied SciencesOnline resources: Click here
In:
Journal of the institution of engineers (India): Series BSummary: Domino logic circuits occupy a prominent circuit design space in the VLSI regime. The primary attributes of the domino circuits, such as high-performance operation, lesser area and lower power consumption, are found to be limited by leakage current, charge sharing and process parameter variations. Various domino logic structures have been presented in the literature to cater to the threats and thereby improve the performance. These design solutions of domino logic are found oriented toward reduction in leakage current, lowering static and dynamic power dissipation, prevention of charge sharing, increase in operating speed and robustness. These metrics are normally achieved through better keeper control mechanism or by restructuring the pull down network or by reducing the redundant switching transitions of the output. This paper sketches the domino logic style-keeper circuit designs found in the literature and reviews them in terms of the techniques employed for performance improvement. These reconfigurations of the basic domino logic circuit keeper structure reports high performance with reduced power consumption and/or improved robustness. The circuit designs and analysis have been carried out using Cadence® Virtuoso using 180 nm technology library.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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Articles Abstract Database
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School of Engineering & Technology Archieval Section | Not for loan | 2022-1671 |
Domino logic circuits occupy a prominent circuit design space in the VLSI regime. The primary attributes of the domino circuits, such as high-performance operation, lesser area and lower power consumption, are found to be limited by leakage current, charge sharing and process parameter variations. Various domino logic structures have been presented in the literature to cater to the threats and thereby improve the performance. These design solutions of domino logic are found oriented toward reduction in leakage current, lowering static and dynamic power dissipation, prevention of charge sharing, increase in operating speed and robustness. These metrics are normally achieved through better keeper control mechanism or by restructuring the pull down network or by reducing the redundant switching transitions of the output. This paper sketches the domino logic style-keeper circuit designs found in the literature and reviews them in terms of the techniques employed for performance improvement. These reconfigurations of the basic domino logic circuit keeper structure reports high performance with reduced power consumption and/or improved robustness. The circuit designs and analysis have been carried out using Cadence® Virtuoso using 180 nm technology library.
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